Mapping for FPGAs with Nonuniform Pin Delays

373 Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections Jason Cong, Yean-Yow Hwang and Songjie Xu Department of Computer Science University of California, Los Angeles, CA 90095 fcong, yeanyow, [email protected] Abstract In this paper we study the technology mapping problem for FPGAs with nonuniform pin delays and fast interconnections. We develop the PinMap algorithm to compute the delay optimal mapping solution for FPGAs with nonuniform pin delays in polynomial time based on the e cient cut enumeration. Compared with FlowMap [5] without considering the nonuniform pin delays, PinMap is able to reduce the circuit delay by 15% without any area penalty. For mapping with fast interconnections, we present two algorithms, an iterative re nement based algorithm, named ChainMap, and a Boolean matching based algorithm, named HeteroBM, which combines the Boolean matching techniques proposed in [2] and [3] and the heterogeneous technology mapping mechanism presented in [1]. It is shown that both ChainMap and HeteroBM are able to signi cantly reduce the circuit delay by making e cient use of the FPGA fast interconnections resources.